ATMEGA328P-15AZ【PDF 52/83 页】MCU AVR 32K FLASH 15MHZ 32-TQFP

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Sheet目录1905

48页 49页 50页 51页 [52页]53页 54页 55页 56页

PIC12(L)F1822/PIC16(L)F1823

DS41413C-page 214

2010-2012 Microchip Technology Inc.

24.4

PWM (Enhanced Mode)

The enhanced PWM mode generates a Pulse-Width

Modulation (PWM) signal on up to four different output

pins with up to 10 bits of resolution. The period, duty

cycle, and resolution are controlled by the following

registers:

PR2 registers

T2CON registers

CCPR1L registers

CCP1CON registers

The ECCP modules have the following additional PWM

registers which control Auto-shutdown, Auto-restart,

Dead-band Delay and PWM Steering modes:

CCP1AS registers

PSTR1CON registers

PWM1CON registers

The enhanced PWM module can generate the following

four PWM Output modes:

Single PWM

Half-Bridge PWM

Full-Bridge PWM (PIC16(L)F1823 only)

Single PWM with PWM Steering mode

To select an Enhanced PWM Output mode, the P1M bits

of the CCP1CON register must be configured

appropriately.

The PWM outputs are multiplexed with I/O pins and are

designated P1A, P1B, P1C and P1D. The polarity of the

PWM pins is configurable and is selected by setting the

bits

CCP1M<3:0>

the

CCP1CON

appropriately.

Figure 24-5 shows an example of a simplified block

diagram of the Enhanced PWM module.

Table 24-9 shows the pin assignments for various

Enhanced PWM modes.

FIGURE 24-5:

EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE

Note 1:

The corresponding TRIS bit must be

cleared to enable the PWM output on the

CCP1 pin.

Clearing the CCP1CON register will

relinquish control of the CCP1 pin.

Any pin not used in the enhanced PWM

mode is available for alternate pin

functions, if applicable.

prevent the generation of an

incomplete waveform when the PWM is

first enabled, the ECCP module waits

until the start of a new PWM period

before generating a PWM signal.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(1)

Duty Cycle Registers

DC1B<1:0>

Clear Timer,

toggle PWM pin and

latch duty cycle

Note

The 8-bit timer TMR1 register is concatenated with the 2-bit internal Q clock, or two bits of the prescaler to create the 10-bit time

base.

PIC16(L)F1823 only.

TRISx

CCP1/P1A

TRISx

P1B

TRISx

P1C(2)

TRISx

P1D(2)

Output

Controller

P1M<1:0>

CCP1M<3:0>

PWM1CON

CCP1/P1A

P1B

P1C(2)

P1D(2)

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